Conventional non-volatile semiconductor memory device (memory) has integrated elements in a two-dimensional plane on a silicon substrate. Increase of memory capacity has been achieved with downsizing a size of one element, however recently the downsizing has been getting more difficult costly and technologically.
In contrast, a collectively processed three-dimensional stacked memory has been proposed. The collectively processed three-dimensional stacked memory is provided with a stacked body including insulating films and electrode films alternately stacked, a silicon pillar piercing the stacked body and a charge storage layer (memory layer) between the silicon pillar and the electrode film, and thereby a memory cell is provided at an intersection of the silicon pillar and respective electrode films.
Furthermore, for example, JP-A 2009-146954 discloses a technique three-dimensionally arraying memory cells by forming a memory hole in a stacked body alternately stacking conductive layers functioning as a control gate of a memory device and insulating layers, and forming a charge storage film on an inner wall of the memory hole and subsequently providing silicon in the memory hole.